Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs)), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) generally include programmable logic blocks which may be configured to implement various operations. Some PLDs also include configurable embedded hardware to support additional operations. However, conventional approaches to configuring such embedded hardware are often cumbersome and unwieldy.
For example, in one approach, embedded hardware and programmable logic blocks may be configured in a shared hardware description language (HDL) hierarchy. However, such a hybrid hardware/programmable logic block HDL hierarchy is complex, time consuming to validate, and may not be easily reused for other applications (e.g., having limited portability).
In another approach, multiple embedded hardware resources may be implemented as a shared block that interfaces with programmable logic blocks in other HDL hierarchies. However, such hardware block sharing can be problematic, as changes to the configuration of one or more shared hardware resources in the block can inadvertently affect the interoperation of the hardware resources with many programmable logic blocks. Such problems are further compounded when additional vendor-provided logic (e.g., soft intellectual property (IP) core logic implemented in programmable logic blocks of the PLD) is used to interface between the embedded hardware and other user-configured programmable logic blocks.
Accordingly, there is a need for an improved approach to configuring hardware resources of a PLD.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.